20230819: new features, changes and fixes since softavrcore version 20230311
============================================================================

Example codes:
 * fix: missing dummy memory added to the ./build-test example
 * chg: code and build system cleanup in the FreeRTOS port (see, ./build-freertos: separate subdirectory, use FreeRTOS as a standalone *.a library, etc)


20230311: new features, changes and fixes since softavrcore version 20230227
============================================================================

Main core:
 * fix: flag update during interrupt entry fixed.
 * fix: interrupt entry is postponed by one instruction during an 0 => 1 transition of the I flag.
 * fix: note: in other words, the next instruction after `sei` or `out 0x3f, rxx` always executed even if the value of the `iflag` input is 1. This is in accordance of the off-the-shelf AVR hardware, and, more importantly, the compiler `avr-gcc` generates such a code which expoits this side effect when stack frames are created.

20230227: new features, changes and fixes since softavrcore version 20230123
============================================================================

Main core:
 * fix: synchronous rst fixed
 * fix: initial states for `state`, `PC` and `init_count` are set to 0 (needed only for simulators)

20230123: new features, changes and fixes since softavrcore version 20200616
============================================================================

Main core:
 * fix: RAM: d_mem/d_read access fixed during interrupt entry
 * fix: I/O: io_re/io_we access fixed during interrupt entry
 * fix: PC stacking during function entry / return now assumes an MSB ordering by default (can be overriden to be compatible with the previous core)
 * fix: LD/ST instructions works now on the register file and I/O space (can optionally be disabled if this feature is not used by the code, saving a few dozens of LUTs/LCs during synthesis)
 * fix: a `define AVR_2WORD_INTERRUPTS is added for supporting avr3* and avr5* architectures (but it is not enabled by default even for those architectures, see avr_core.v)
 * chg: MEM_OFFSET is changed to 0 from 96. The RAM attached to the CPU therefore "wraps around", but the address (dmem_a, seen by the RAM) remains now the same as it is seen by the AVR code running on the CPU
 * new: sleep mode and SLEEP instruction is now available (this instruction halts the CPU until an interrupt arrives if I=SREG[7] is set in advance)
 * new: watchdog reset (WDR) instruction is now available: it puts the CPU into "WDR" mode for one cycle (see the output avr_core.mode[1:0])
 * new: CPU mode with a mode[1:0] output is now available, exposing the SLEEP state (2'b01) and the WDR instruction (2'b10) to outer peripherals
 * new: some optimizations in stage1 (instruction fetch)
 * new: synchronous reset of the CPU is now available 
 * new: automatic interrupt acknowledgement is supported via the avr_core.in_ieack[] output 
 * new: note: this interrupt acknowledgement works for the non-zero interrupts only, so a CPU reset sent via interrupts are not acknowledged in this manner

Peripherals:
 * fix: minor fixes in the avr_systick.v SysTick timer
 * new: the SysTick timer (avr_systick.v) supports automatic interrupt acknowledgement using its avr_systick.ack input
 * new: avr_io_crc.v: a new 32-bit CRC calculator unit (now only with a fixed polynomial) is now available

Example codes:
 * new: a FreeRTOS port is now available with two simple tasks (including sleeping in the idle state), it employs the SysTick timer peripheral (see above)
 * new: RAM size (via __DATA_REGION_LENGTH__) is passed to the linker in order to check bss/data/heap sizes during linking
 * new: some pre-defined symbols (like __DATA_REGION_LENGTH__) are exploited in the crt0.S execution startup routine